Dynamic Power Saving for Multiplier
Keywords:
Multiprecision, Dynamic Voltage Scaling, Higher-Precision Multiplications, razor flip-flops, DVS.Abstract
This paper is related to development of a multiprecision (MP) reconfigurable multiplier with dynamic voltage scaling. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. Given the user’s requirements a dynamic voltage/frequency scaling management unit configures the multiplier to operate at the proper precision and frequency. Adapting to the run-time workload of the targeted application, razor flip-flops together with a dithering voltage unit then configure the multiplier to achieve the lowest power consumption. Adapting to the run-time workload of the targeted application, razor flip-flops combine with a dithering voltage unit, because of this the multiplier is able to achieve the lowest power consumption. Use of single switch dithering voltage unit and razor flip-flops help to minimize the safety margins in voltage and overhead in DVS.
References
[1] S. Das, C. Tokunaga, S. Pant, W.-H. Ma, S. Kalaiselvan, K. Lai, D. M. Bull, and D. T. Blaauw, “RazorII: In situ error detection and correction for PVT and SER tolerance,” IEEE J. Solid-State Circuits,vol. 44, no. 1, pp. 32–48, Jan. 2009.
[2] S.-R. Kuang and J.-P. Wang, “Design of power-efficient configurable booth multiplier,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 3, pp. 568–580, Mar. 2010.
[3] A. Youssef, M. Anis, and M. Elmasry, “A comparative study between static and dynamic sleep signal generation techniques for leakage tolerant designs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,vol. 16, no. 9, pp. 1114–1126, Sep. 2008.
[4] R. Min, M. Bhardwaj, S.-H. Cho, N. Ickes, E. Shih, A. Sinha, A. Wang,and A.Chandrakasan, “Energy-centric enabling technologies for wireless sensor networks,” IEEE Wirel. Commun., vol. 9, no. 4, pp. 28–39, Aug. 2002.
[5] F. Carbognani, F. Buergin, N. Felber, H. Kaeslin, and W. Fichtner, “Transmission gates combined with level-restoring CMOS gates reduce glitches in low-power low-frequency multipliers,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 7, pp. 830–836, Jul. 2008.
[6] Xiaoxiao Zhang, Farid Boussaid,and Amine Bermak,“32 Bit×32 Bit Multi precision Razor- Based Dynamic Voltage Scaling Multiplier With Operands Scheduler”IEEE Trans. on VLSI SYSTEMS, VOL. 22, NO. 4, APRIL 2014 759.
[7] K.Harika, B.V.Swetha, B.Renuka, D.Lakshman Rao, S.Sridhar,”Analysis of Different Multiplication Algorithms & FPGA Implementation” IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 2, Ver. I (Mar-Apr. 2014), PP 29-35.
[8] Shruti Hathwalia, Sansar Chand Sankhyan,”A NOVEL APPROACH FOR DISPLAYING DATA ON LCD USING FPGA” International Journal of Technical Research and Applications e-ISSN: 2320-8163, www.ijtra.com Volume 1, Issue 4 (sept-oct 2013), PP. 48-51.
[9] Mounir Zid, Carlo Pistritto, Rached Tourki and Alberto Scandurra,”A NEW N-FOLD FLIP-FLOP WITH OUTPUT ENABLE”International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.2, June 2013.
[10] Shivangi Tiwari, Shweta Singh, Nitin Meena,”FPGA Design and Implementation of Matrix Multiplication Architecture by PPI-MO Techniques”International Journal of Computer Applications (0975 – 8887) Volume 80 – No1, October 2013.
[11] Jitha K T, Remya K R,”DESIGN OF POWER AND DELAY EFFICIENT 32 BIT X 32 BIT MULTI-PRECISION MULTIPLIER WITH OPERANDS SCHEDULER”IJRET: International Journal of Research in Engineering and Technology, Volume: 04 Issue: 02, Feb-2015.
[12] Chinthanai Selvi. S, Vigneshwari Rajagopal .R,” RAZOR BASED DVS USING MULTIPRECISION AND OPERAND SCHEDULING FOR FAST MULTIPLICATION”, International Journal on Applications of Information and Communication Engineering Volume 1: Issue 1: January 2015.
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