An Effective Way to Minimize the Area and Delay of Carry Select Adder
Keywords:
Carry select adder (CSLA), BEC-based carry select adder, SQRT, ADP.Abstract
Within this paper, the logic functions engaged in conventional carry select adder (CSLA) and BEC-based carry select adder (CSLA) i.e., binary to excess-1 converter based carry select adder are estimated to study the data dependence and to recognize unneeded logic functions. We have removed all the unnecessary logic functions built-in in the conventional CSLA and proposed a new logic creation for CSLA. In the proposed method, the carry select (CS) function is designed before the calculation of final-sum which is dissimilar from the conventional approach. Bit patterns of two expecting carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. A able CSLA design is acquired using better logic units. The proposed carry selects adder (CSLA) design occupies significantly less area and delay than the freshly proposed BEC-based carry select adder. Due to the slight carry-output delay, the proposed CSLA design is a high-quality nominee for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA occupy almost 35% less area–delay–product (ADP) than the BEC-based SQRT-CSLA, which is best between the existing SQRT-CSLA designs, for the different input bit-widths.
References
[1] O. J. Bedrij, “Carry-select adder,” IRE Trans. Electron. Comput., pp. 340–344, 1962.
[2] J.Sklansky, “Conditional-Sum Addition Logic,” IRE Trans. Electron. Comput., vol. EC-9, pp.226-231, 1960.
[3] T. Y. Ceiang and M. J. Hsiao, “Carry-select adder using single ripple carry adder,” Electron. Lett., vol. 34, no. 22, pp. 2101–2103, Oct. 1998.
[4] Y. Kim and L.-S. Kim, “64-bit carry-select adder with reduced area, “Electron. Lett., vol. 37, no. 10, pp. 614–615, May 2001.
[5] M.Alioto et.al, “A Gate Level Strategy To Design Carry Select Adders,” ISCAS 2004.
[6] Behnam Amelifard et.al “Closing the Gap between Carry Select Adder and Ripple Carry Adder,” Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED’05), 2005.
[7] Y. He, C. H. Chang, and J. Gu, “An area-efficient 64-bit square root carry select adder for low power application,” in Proc. IEEE Int. Symp.CircuitsSyst., 2005, vol. 4, pp. 4082–4085.
[8] B. Ramkumar, H.M. Kittur, and P. M. Kannan, “ASIC Implementation Of Modified Faster Carry Save Adder,” Eur. J. Sci.Res., vol. 42, no. 1, pp. 53–58, 2010.
[9] B. Ramkumar and H.M. Kittur, “Low-power and area-efficient carry-select adder,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2,pp. 371–375, Feb. 2012.
[10] I.-C. Wey, C.-C. Ho, Y.-S. Lin, and C. C. Peng, “An area-efficient carry select adder design by sharing the common Boolean logic term,” in Proc.IMECS, 2012, pp. 1–4.
[11] S.Manju and V. Sornagopal, “An efficient SQRT architecture of carry select adder design by common Boolean logic,” in Proc. VLSI ICEVENT, 2013,pp. 1–5.
[12] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs, 2nd ed. New York, NY, USA: Oxford Univ. Press, 2010.
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