An Overview of Delay-Area Efficient Carry-Select Adder (International Journal of Advanced Research in Science, Management and Technology, 2021)
An adder with superb area & speed is one of the most main areas of study in VLSI system design. With finest area & speed, reducing the power consumption is also main area of research in VLSI system design. Here we use a carry select adder design for the realization of fast adder. There are several choices for design of carry select adder. Carry select adder (CSLA) is one of the fastest adders and used in many data processing processors to achieve fast arithmetic function. From the construction of the CSLA, we come to know that there is an choice for reducing the area and power consumption in the CSLA. This work uses an easy and planned gate-level adjustment to considerably reduce the area and power consumption of CSLA. We compare some of these techniques with existing conventional fast adder design to verify its efficiency.
Keywords: VLSI system design, CSLA, power consumption, conventional fast adder