Performance Evaluation of Network on Chip Architectures Using Network Simulator-2 (International Journal of Advanced Research in Science, Management and Technology, 2016)
A new chip design paradigm Network on Chip (NoC), proposed by many research groups is an important architectural choice for future System on Chips (SoCs). Various proposed NoC architecture attempts to address different component level architectures with specific interconnection network topologies and routing techniques. For NoC-based systems, performance could be modelled at different levels of abstraction. In the same context, improving systems performance could be achieved at different design phases. The interconnections among multiple cores on a chip have a significant impact on communication and performance of the chip design in terms of end-to-end delay, throughput, and packets loss ratio. Therefore, it is worthwhile studying the different characteristics of different topologies. Network Simulator (NS) is a name for series of discrete event network simulators, specifically; NS-1, NS-2 and NS-3. These simulators are used in the simulation of routing protocols, among others, and are heavily used in ad-hoc networking research, and support popular network protocols, offering simulation results for wired and wireless networks. NS-2 is primarily UNIX based and it uses Tool Command Language (TCL) as its scripting language.
Keywords: Network on Chip (NoC), System on Chips (SoCs), Network Simulator (NS), UNIX, Tool Command Language (TCL).