(untitled) (International Journal of Advanced Research in Science, Management and Technology, 2022)
A digital adder with best area & speed is one of the major areas of study in VLSI system design. With finest area & speed, reducing the power utilization is also main area of research in VLSI system design. Our approach uses a carry select adder design for the realization of fast adder. There are various options for implementation of carry select adder. Carry select adder (CSLA) is one of the fastest adders and in many data processing processors to achieve fast arithmetic function. From the construction of the CSLA, it is clear that there is an option for reducing the area and power utilization in the CSLA. This work uses an easy and well-organized gate-level modification to considerably reduce the area and power consumption of CSLA. We compare some of these techniques with existing conventional fast adder design to verify its efficiency.